1. Field of the Invention
The present invention relates to a data transfer system and, more particularly, to a data transfer system, in a system whose operation timing after the acceptance of interruption processing is required to be stable, which has a function of suspending data transfer to give priority to interruption processing when an interruption occurs during the data transfer and preventing an error caused by the suspension of data transfer.
2. Description of the Related Art
In a data transfer system in which data to be transferred is divided and divisionally transferred several times, when interruption processing occurs during data transfer, it is a common practice to maintain the data transfer state until the transfer of the data being transferred is completed and proceed to interruption processing operation after the completion of the data transfer processing, thereby preventing data transfer error from occurring.
FIG. 6 shows structure of a conventional data transfer system of this kind. The conventional data transfer system shown in FIG. 6 includes a data transmission unit 210 for transmitting data and a data reception unit 220 for receiving data transmitted by the data transmission unit 210. The data transmission unit 210 includes an arithmetic unit 211, a storage unit 212, a transfer state control unit 213, a transfer data storage unit 214 and an interruption control switch 215. The data reception unit 220 includes a transfer control unit 221, a received data accepting unit 222 and a data storage unit 223. With the above-described structure, data whose arithmetical processing has been conducted by the arithmetic unit 211 of the data transmission unit 210 is transferred to the data reception unit 220.
When transferring no data, the data transmission unit 210 stores data whose arithmetical processing has been conducted at the arithmetic unit 211 in the transfer data storage unit 214 to enter a next processing waiting state. When data transfer is started, first, a data reading timing signal 112 is output from the transfer state control unit 213 and sent to the transfer control unit 221 of the data reception unit 220. In addition, the data held at the transfer data storage unit 214 is bit-serially output in synchronization with the data reading timing signal 112 output by the transfer state control unit 213, so that serial data 104 is transferred to the data reception unit 220. The data reception unit 220 receives the transferred data 104 and stores the same at the received data accepting unit 222. As a result of the foregoing operation, data transfer from the data transmission unit 210 to the data reception unit 220 finishes.
While data transfer from the data transmission unit 210 to the data reception unit 220 is under way, when an external interruption signal 101 is applied, the interruption signal 101 is held in the interruption control switch 215 based on a control signal supplied from the transfer state control unit 213 until the data transfer is completed. Then, after the completion of the data transfer, switching of the interruption control switch 215 is conducted such that the interruption signal 101 is transmitted to the arithmetic unit 211. This prevents data transfer error from occurring which is caused by interruption processing occurring during data transfer.
One of the above-described conventional data transfer systems is, for example, a data transfer system disclosed in Japanese Patent Laying Open (Kokai) No. Showa 61-289749, entitled "Serial Data Transfer Device".
FIG. 7 shows structure of a transmission unit for use in the data transfer system recited in the above-described literature. As illustrated in FIG. 7, the transmission unit according to the present related art includes a transfer register 201, a mode control circuit 202, a transfer counter 203, a flag circuit 204 and a mode hold circuit 205. The mode control circuit 202 is supplied with a transfer start signal 110 and an output of the mode hold signal circuit 205. The mode hold circuit 205 is supplied with a mode designation signal 111. The transfer register 201 is supplied with a data signal 108 and a control signal output from the mode control circuit 202.
The transfer register 201 receives input of the data signal 108 to transfer data bit-serially based on a control signal. In other words, the transfer register outputs the data signal 108 as serial data 109. The transfer counter 203 counts a volume of output data transfer. The flag circuit 204 is set by the externally supplied transfer start signal 110 and is reset upon detection of overflow of the transfer counter 203. With the foregoing structure, when the flag circuit 204 detects overflow of the transfer counter 203, data is read on a bus line, so that transfer of the serial data 109 is completed. On the other hand, during data transfer, control operation is being conducted such that an operation mode is not switched, thereby disabling intervention of other interruption processing to prevent an error from occurring during data transfer.
In practical use, however, there exists such a system as is incapable of waiting for data transfer to end when an interruption occurs during data transfer, that is, a system required to synchronize with an interruption instruction. To this kind of system, conventional art is not directly applicable in which interruption processing is waited for until the end of data transfer in order to prevent the above-described transfer error. As an example of a system of this kind, a vertical deflection correction system on a horizontal/vertical synchronization signal frequency variable type display will be described. Vertical deflection correction in this system aims to conduct correction of screen display position, screen size, and distortion of a display screen.
In vertical deflection correction by a conventional vertical deflection correction system, there are, as synchronization signals of image, a vertical synchronization signal (a signal for determining a vertical position of a scanning line on a screen) and a horizontal synchronization signal (a signal for determining a horizontal position of a scanning line on a screen). Through the generation of a correction current in response to each synchronization signal, a scanning line is controlled to correct a display screen. A correction signal for a vertical position control signal of a common scanning line is a triangular wave signal in which a low voltage, for example, denotes an upper part of the screen and an increasing voltage denotes that a scanning line shifts toward a lower part of the screen. As a voltage of a correction signal increases gradually, a scanning line is moved downward on the screen. At the time point when the voltage increases to the maximum, that is, at a time point when the scanning line is moved to the lowermost end of the screen, the voltage is decreased at a breath in synchronization with a vertical synchronization signal to start subsequent scanning from the uppermost end of the screen. While a voltage is being decreased, no scanning line is displayed on the screen. In addition, various arithmetical processing is conducted using a triangular wave signal of a correction signal. Deformation of a waveform of a triangular wave therefore leads to control for the above-described respective corrections etc.
When conducting arithmetical processing and data transfer processing (correction waveform output) repeatedly, such a data transfer system as the above-described vertical deflection correction system needs to forcibly suspend arithmetical processing and data transfer processing, conduct interruption processing in response to a vertical synchronization signal and conduct all the processing thereafter, with a vertical synchronization signal as a starting point. To control a horizontal/vertical synchronization signal frequency variable type display, it should be operated at various frequencies of a synchronization signal. There is therefore no knowing at which timing of data processing a vertical synchronization signal is applied, and there is accordingly a possibility of occurrence of an interruption during data transfer.
In this case, if no switching to an interruption mode is made in synchronization with a vertical synchronization signal (interruption signal) in order not to cause a data transfer error as in the above-described data transfer system shown in FIGS. 6 and 7, a time from the application of the above-mentioned interruption signal until entering an interruption operation mode will appear as a variable time for starting subsequent data processing. In other words, if a time before processing starts after the application of a vertical synchronization signal is inconstant, a scanning line will be displaced on a screen to the extent of variation of a time before data transfer ends after an interruption signal is applied and the displacement will appear as jitter. On an actual screen, display dots fluctuate vertically as a result.
As described in the foregoing, in a case where interruption processing is generated during data transfer, in order to prevent an error which is derived from imperfect data transfer caused as a result of the suspension of the data transfer by the interruption, a conventional data transfer system is controlled such that the interruption processing generated during the data transfer waits for the data transfer to end. For a system required to have stable operation timing after the acceptance of interruption processing such as a vertical deflection correction system for use in generation and adjustment of a vertical synchronization signal of a display, however, control for waiting interruption processing can not be conducted as it is because with such control, a time for shifting to an interruption operation mode, from the input of an interruption signal until the end of data transfer output, will be a variable time for starting data processing.
In addition, in such a system required to have constant operation timing after the acceptance of interruption processing as described above, if, at the time of the generation of interruption processing during data transfer, the data transfer is suspended to execute the interruption processing in order to give higher priority to stabilization of operation timing, occurrence of the above-described data transfer error will be invited.